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SLEEP mode
The block disconnects power to CPU, and the internal logic, with the exception of
the wake-up logic. Activating the SLEEP mode requires two independent power
sources. One of the two power sources supplies the power for the wake-up logic.
The other power source supplies the CPU and internal logic, and should be
controlled for power on/off. In SLEEP mode, the second power supply source for the
CPU and internal logic will be turned off. The wake-up from SLEEP mode can be
issued by EINT[15:0].
In SLEEP mode, VDDi, VDDiarm, VDDMPLL and VDDEPLL will be turned off, and are
controlled by PWREN. If the PWREN signal is activated (H), VDDi and VDDiarm are
supplied by an external voltage regulator. If PWREN pin is inactive (L), VDDi and
VDDiarm are turned off.
In Power_OFF mode 1.2V have to be supplied to the VDD alive pin, and it is also
necessary to provide the I/O-voltages of 1.8V/3.3V. Therefore the LDO, which
supplies VDD alive will not be switched off.
The following describes the sequence of entering SLEEP mode:
1
2
3
4
5
6
One of the SLEEP Mode entering events is triggered by the system software or by
the hardware.
System controller requests bus controller to finish pending transaction.
Bus controller sends acknowledgement to system controller after bus
transactions are completed.
System controller requests memory controller to enter self-refresh mode,
preserving SDRAM contents.
System controller waits for self-refresh acknowledgement from memory
controller.
After receiving the self-refresh acknowledge, disables the XTAL and PLL
oscillation and also disables the external power source for the internal logic by
asserting the PWR_EN pin to low state. The PWR_EN pin is the regulator disable
control signal for the internal logic power source.
The SLEEP mode exit sequence is as follows.
www.digiembedded.com
1
2
System controller enables external power source by deasserting PWR_EN to high
state and initiates power settle down programmable through a register in the
PWRSETCNT field of RSTCON register.
System controller releases the System Reset (synchronously, relatively to the
system clock) after the power supply is stabilized.
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